Self-aligned conductive lines for fet-based magnetic random access memory devices and method of forming the same

ABSTRACT

A conductive line structure for a field effect transistor (FET) based magnetic random access memory (MRAM) device includes a lateral metal strap conductively coupled to a lower metallization line. A magnetic tunnel junction (MTJ) stack is formed on the metal strap, and a metal shield is formed over the MTJ stack, the metal shield being self-aligned with respect to the metal strap. An upper metallization line is conductively coupled to the metal shield, wherein the metal shield serves as an etch stop during the formation of the upper metallization line.

TECHNICAL FIELD

The present invention relates generally to semiconductor deviceprocessing and, more particularly, to self-aligned conductive lines forFET-based magnetic random access memory devices and method of formingthe same.

BACKGROUND OF THE INVENTION

Magnetic (or magneto-resistive) random access memory (MRAM) is anon-volatile random access memory technology that could potentiallyreplace the dynamic random access memory (DRAM) as the standard memoryfor computing devices. The use of MRAM as a non-volatile RAM willeventually allow for “instant on” systems that come to life as soon asthe system is turned on, thus saving the amount of time needed for aconventional PC, for example, to transfer boot data from a hard diskdrive to volatile DRAM during system power up.

A magnetic memory element (also referred to as a tunnelingmagneto-resistive, or TMR device) includes a structure havingferromagnetic layers separated by a non-magnetic layer (barrier), andarranged into a magnetic tunnel junction (MTJ). Digital information isstored and represented in the memory element as directions ofmagnetization vectors in the magnetic layers. More specifically, themagnetic moment of one magnetic layer (also referred to as a referencelayer) is fixed or pinned, while the magnetic moment of the othermagnetic layer (also referred to as a “free” layer) may be switchedbetween the same direction and the opposite direction with respect tothe fixed magnetization direction of the reference layer. Theorientations of the magnetic moment of the free layer are also known“parallel” and “antiparallel” states, wherein a parallel state refers tothe same magnetic alignment of the free and reference layers, while anantiparallel state refers to opposing magnetic alignments therebetween.

Depending upon the magnetic state of the free layer (parallel orantiparallel), the magnetic memory element exhibits two differentresistance values in response to a voltage applied across the tunneljunction barrier. The particular resistance of the TMR device thusreflects the magnetization state of the free layer, wherein resistanceis “low” when the magnetization is parallel, and “high” when themagnetization is antiparallel. Accordingly, a detection of changes inresistance allows a MRAM device to provide information stored in themagnetic memory element (i.e., a read operation). In addition, a MRAMcell is written to through the application a bi-directional current in aparticular direction, in order to magnetically align the free layer in aparallel or antiparallel state.

A practical MRAM device may have, for example, a cross point cell (XPC)configuration, in which each cell is located at the crossing pointbetween parallel conductive wordlines in one horizontal plane andperpendicularly running sense lines in another horizontal plane. Thisparticular configuration is advantageous in that the layout of the cellshelps to increase the array cell density of the device. However, onedifficulty associated with the practical operation of a cross-point MRAMarray relates to the sensing of a particular cell, given that each cellin the array is coupled to the other cells through several parallelleakage paths. The resistance seen at one cross point equals theresistance of the memory cell at that cross point in parallel withresistances of memory cells in the other rows and columns, and thus canbe difficult to accurately measure.

Accordingly, MRAM devices are also fabricated with a field effecttransistor (FET) based configuration. In the FET-based configuration,each MRAM cell includes an access transistor associated therewith, inaddition to an MTJ. By keeping the access transistors to cells not beingread in a non-conductive state, parasitic device current is preventedfrom flowing through those other cells. The tradeoff with the FET-basedconfiguration versus the XPC-based configuration is the area penaltyassociated with the location of the access transistors and additionalmetallization lines.

In a conventionally formed FET-based MRAM device, the MTJ is typicallyformed over a conductive metal strap that laterally connects the bottomof the MTJ to the access FET (through a via, metallization line andcontact area stud). In addition, a relatively thick layer of metalhardmask is formed on the top of the MTJ such that a trench etching stepmay be used to form the upper metallization layer for connection to thecell. If the metal hardmask is too thin, the formation of the trench forthe upper metallization layer could also end up exposing the metal strap(through a phenomenon such as “microtrenching”, for example). This wouldin turn cause the subsequently formed upper metallization material fillto contact the metal strap, thus shorting across the MTJ and ruining thememory element. On the other hand, having too thick a hardmask willincrease the distance between the upper metallization layer and the MTJ,thereby increasing the level of current needed to generate the magneticfield for switching the state of the magnetic memory element.

Because of the continuing trend of decreasing device ground rules andsmaller wiring sizes, it is therefore desirable to be able to bring theupper metallization level of an FET-based MRAM device closer to the MTJelement, but without increasing the risk of shorting the uppermetallization level to the metal strap portion of the device.

SUMMARY OF INVENTION

The foregoing discussed drawbacks and deficiencies of the prior art areovercome or alleviated by a self-aligned, protective conductive linestructure for a field effect transistor (FET) based magnetic randomaccess memory (MRAM) device including a lateral metal strap conductivelycoupled to a lower metallization line. A magnetic tunnel junction (MTJ)stack is formed on the metal strap, and a metal shield is formed overthe MTJ stack, the metal shield being self-aligned with respect to themetal strap. An upper metallization line is conductively coupled to themetal shield, wherein the metal shield serves as an etch stop during theformation of the upper metallization line.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring to the exemplary drawings wherein like elements are numberedalike in the several Figures.

FIG. 1 is a cross sectional view of a conventionally formed, FET-basedMRAM device.

FIG. 2 is a detailed view of the formation of an upper metallizationlevel trench of the MRAM device of FIG. 1, particularly illustrating“microtrenching” phenomenon.

FIGS. 3(a) through 3(f) illustrate an exemplary process for forming anFET-based magnetic random access memory device having self-alignedconductive lines, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Disclosed herein is a method of forming an FET-based magnetic memorydevice, in which a self-aligned metal shield is formed in conjunctionwith a conductive strap located at the bottom of the magnetic memoryelement. Again, the metal strap is used to couple the memory element toan access transistor disposed beneath the element. The metal shield thusprovides protection for the strap during later processing steps,particularly that step in which an upper metallization trench is etchedfor contacting the top of the magnetic memory element. Such protectionprevents shorting of the memory element, as well as provides theadditional benefit of allowing the upper metallization wires to beformed closer to the top memory element. This further results in relaxedrequirements with respect to the amount of current needed to switch thememory element.

Referring initially to FIG. 1, there is shown a cross sectional view ofa conventionally formed, FET-based MRAM device 100. More specifically,FIG. 1 illustrates a portion of an FET-based memory element 102 disposedbetween a lower metallization level and an upper metallization level. Inthe example depicted, the lower metallization level corresponds to thefirst metallization level (M1) of the MRAM device 100, while the uppermetallization level corresponds to the second metallization level (M2)of the MRAM device 100. However, one skilled in the art will recognizethat the individual memory elements could also be formed between otherlayers within the device 100 (e.g., between M2 and M3).

As is shown in FIG. 1, the memory element 102 includes an MTJ stackhaving a lower magnetic layer 104 with a non-magnetic layer (e.g., anoxide) and upper magnetic layer formed thereatop (shown collectively aslayer 106). Although the cell 102 is located at a correspondingintersection between a wordline 108 and a bitline 110, the bottomportion of the cell 102 is not in direct electrical contact withwordline 108, unlike the XPC configuration. Instead, the cell 102 isformed atop metal strap 112, which serves to interconnect the cell 102to lower level metallization line 114 through via stud 116. In turn,line 114 completes the connection of the cell 102 to an associatedsubstrate-level access transistor (not shown) through contact area stud118.

As indicated previously, the conventional FET-based cell configurationof FIG. 1 provides for a relatively thick metal hardmask 120 (e.g., onthe order of about 1700 angstroms (Å)) that serves as an interconnectbetween bitline 110 and the top layer of cell 102. The remaining areasof device 100, generally indicated at 122, represent insulating (e.g.,dielectric) layers for interlevel isolation. It should be noted at thispoint that the M2 level of the device 100 shown in FIG. 1 (that is, theportion of the figure above the dashed line) has been rotated by 90° forpurposes of illustration, which will become more apparent hereinafter.One skilled in the art will recognize that, since the metallizationlines at M1 and M2 are orthogonal to one another, the bitline 110 at M2would actually be disposed horizontally along the top of FIG. 1. Inaddition, FIG. 1 also illustrates a periphery region 124 of device 100,in order to illustrate the relationship between lower metallizationlevel M1, upper metallization level M2, and connecting via stud V1.

As also described previously, the existing methodology utilizes arelatively large thickness for the metal hardmask 120 on top of the TJelement, such that a timed trench etch can be used to define the M2bitline 100. The etch is intended to terminate after reaching the metalhardmask 120, but before the metal strap 112 is exposed. With the everincreasing desire for device miniaturization and power reduction, adecreased wiring size results in a corresponding need to reduce thedistance between the bitline and the MTJ stack. However, as a result ofunavoidable etch nonuniformities and the microtrenching effect, the M2level cannot be brought arbitrarily close to the top of the MTJ stackwithout the risk of shorting to the metal strap. The microtrenchingeffect is illustrated in FIG. 2. It is believed that, during the etchingprocess for the M2 trench formation, the outer edges thereof receiverelatively greater ion bombardment due charging effects along the edges.Thus, the additional etching at the outer edges 126 of the M2 trench(extending beyond the outer edges of hardmask 120) result in anirregular trench shape in which there is less clearance between M2 andthe metal strap 112 at the outer edges. As such, a significant reductionin the thickness of the hardmask 120 increases the risk of a deviceshort.

Therefore, in accordance with an embodiment of the invention, there isdisclosed an FET-based magnetic random access memory device havingself-aligned conductive lines such that an additional metal hardmaskformed above the memory element has the same shape as the metal strapbeneath the memory element. The metal hardmask thereby serves as ashield that prevents the M2 trench formation from reaching a depth belowthe top of the memory element and shorting to the metal strap.Accordingly, the metal shield allows for the formation of a much thinnerMTJ metal hard mask and concomitant reduction of the distance between M2and the MTJ, thus resulting in a higher magnetic field strength for agiven amount of bitline current. In addition, the process allows forbetter pattern transfer fidelity with regard to the MTJ hardmask etchingbecause a thinner hardmask is used.

An exemplary processing sequence is illustrated in FIGS. 3(a) through3(f). For purposes of simplicity, the FET and other associatedvias/connections below the M1 metallization level are omitted. Generallyspeaking, the processing steps in forming the device up to the partiallycompleted structure shown in FIG. 3(a) may be produced in accordancewith conventional techniques. In particular, the lines formed at the M1level of metallization are preferably comprised of copper filledtrenches 302 defined in a dielectric 304 such as silicon dioxide. Inaddition, a metal strap via 306 is formed in another dielectric 308through a metal damascene process.

First, an underlayer of metal 310 used in the formation of the metalstrap. Then, the active magnetic stack materials (denoted collectivelyby 312) are deposited on the metal underlayer 310, followed by aconducting hardmask capping layer 314. In a preferred embodiment, thestrap metal underlayer and hardmask capping layer are tantalum (Ta) ortantalum nitride (TaN) based materials. However, other similar suitablematerials such as titanium nitride (TiN), tungsten (W), platinum (Pt),and the like, may also be used. In addition, the initial thickness ofthe hardmask capping layer 314 is preferably selected at about 500 Å,although this may be adjusted to be within a range of about 100 Å toabout 1500 Å, depending on the particular needs of the specific memoryelement design. It should be noted that the existing device processtypically utilizes a very thick metal hardmask capping layer (e.g.,about 1700 Å).

The exemplary process flow embodiment of the present invention processflow deviates from the conventional processing in a manner shown in FIG.3(b). A photoresist (not shown) (or photoresist plus a suitablehardmask) is used to define the tunnel junction 316 by etching throughthe capping layer 314 and the magnetic stack layers 312, but not throughthe strap metal underlayer 310. This photolithography and etching stepthus defines a memory element in a region suitable for switching bymagnetic fields from the associated M1 and M2 wires (i.e., the wordlineand bitline). Because the present invention embodiment uses a relativelythin metal hardmask capping layer 314, the memory element definitionetch is much simpler, thereby allowing a greater fidelity in patterntransfer. After the etch through the magnetic layers 312, a dielectricfilm 318 is deposited to encapsulate the tunnel junction memory element316.

Considerable flexibility is contemplated with regard to the choice ofdielectric materials for the dielectric film 318 (e.g., silicon nitride,silicon oxide, silicon carbide, low-K materials, etc.), so long as thedielectric is suitable for a subsequent polish by chemical-mechanicalplanarization (CMP) or planarization by etchback. Thus, a dielectricmaterial may be chosen that optimizes the performance of the memoryelement, as opposed to concerns with process compatibility. After thedielectric deposition, a CMP step is used to polish away the dielectricatop the tunnel junction metal hardmask 314, leaving (for example) onlyabout 200 Å of the original 500 Å of hardmask thickness. In alternativeembodiments, (with different metal hardmask materials and thicknesses),the remaining thickness may vary depending on the effectiveness of theCMP. It will be appreciated, however, that the choice of metal hardmaskmaterial and thickness is not a significant issue with regard to thesuccess of the process flow, and affects device performance only to theextent of the spacing that ultimately results between the subsequentlyformed M2 wire and the memory element.

As shown in FIG. 3(c), the CMP polish step is followed by the depositionof a metal “shield” layer 320, and well as any appropriate hardmasklayers 322 used for subsequent patterning of the shield layer 320. In apreferred embodiment, the shield layer 320 is also Ta or TaN, with athickness of about 200 Å. However, alternative embodiments may utilizeother materials and thicknesses for the shield material, so long as theycan be readily etched yet also serve as suitable etch stops when inenvironments tailored for etching dielectric materials such as siliconoxide, silicon nitride, low-K materials, etc. Again, it is desirable tobe able to keep the thickness of the shield layer 320 to a minimum, asthis will affect the distance between the M2 wire and the memoryelement. As also illustrated in FIG. 3(c), a dielectric film 322 ofsuitable thickness may be used as a hardmask on top of the shield layer320, if photoresist is not suitable alone.

Referring now to FIG. 3(d), following the deposition of the shield andmask layers, the shape of the metal strap is patterned through theshield layer material 320, the intermediate dielectric 318, and thestrap metal underlayer material 310, in a self-aligned fashion thatkeeps the resulting metal shield 324 overlapped with the lateral metalstrap 326. Although this patterning is generally implemented throughreactive ion etching, it could be accomplished through other techniquessuch as wet chemical etching or ion milling, for example. After thestrap patterning etching step, a wet chemical etch clean or othersuitable dry chemical etch clean can be performed without damage to thetunnel junction memory element. Since the memory element is completelyencapsulated at this point, it will not degrade as the result of anychemical cleans that may be applied in order to improve adhesion ofsubsequent layers to be deposited.

As shown in FIG. 3(e), if necessary, an additional layer ofencapsulating adhesive dielectric 328 is formed over the top of theshield 324 (and along the sides of the shield 324 and strap 326). Then,an upper metallization (M2) level dielectric 330 is deposited, which mayinclude for example silicon nitride, silicon oxide, silicon carbide,low-K materials, etc., or multilayers comprising one or more of suchmaterials. Following deposition of the M2 level dielectric, a CMP stepis performed to planarize the top surface thereof down to a suitabledistance from the top of the shield 324. This distance is generallydetermined by the initial choice of M2 dielectric thickness and the CMPpolish time, and will thus result in automatic definition of the M2metal thickness.

Finally, FIG. 3(f) illustrates the formation and fill of the M2 metaltrench (i.e., the formation of the cell bitline), wherein the bitline332 makes contact to the top of the memory element 316 through theconductive shield 324. Again, for purposes of illustration, the M2trench is shown rotated 90 degrees with respect to the lower devicelevels. It will be appreciated that the distance between the bitline 332and the top of the memory element stack 316 is defined by the thicknessof the TaN tunnel junction hardmask 314 atop stack 316, and thethickness of the shield 324. Since in the illustrated embodiment, thetotal thickness of the hardmask 314 and the shield 324 is on the orderof about 400 to about 500 Å, the bitline 332 is disposed relativelyclose to the memory element 316, thereby facilitating low-currentwriting of the memory element. Moreover, since the shield 324 serves asan etch stop for the M2 trench, the deposition of the M2 fill does notshunt the memory element stack 316 by contacting the strap 326.

It will thus be appreciated that the use of the protective upper shieldmetal is facilitates the etching of the M2 trench in the dielectric 330with a well-defined etch stop at a set distance above the metal strap326. Through appropriate selection of metal shield materials, M2-leveldielectrics, and RIE process parameters, an extremely high selectivitybetween the dielectric and the metal shield may be achieved, such thatthe M2 trench etch stops sharply on the thin shield metal. The M2 trenchmay then be filled in with metal (for example, through a copperdamascene technique), thereby resulting in the self-aligned structuresuch as that shown in FIG. 3(f). In addition, the process enhances thepattern transfer fidelity when etching the magnetic memory element, inthat it allows the use of thinner mask materials. The improved patterntransfer results in improved uniformity for the array of memoryelements, and thereby improves yield and allows scaling to smallerdimensions.

Although the formation of V1 vias have not been described in exemplaryprocess flow, they may be easily added through the use of existingtechniques known to those skilled in the art. Again, prior to theaddition of metal in the M2 trenches (and any V1 vias), a wet or drychemical cleaning step may be added to improve contact reliability andconductivity. Because the shield structure 324 completely covers thetunnel junction stack 316 and any sidewall residue that may form duringthe MTJ etch, the shield structure 324 effectively protects the tunneljunction stack 316 from degradation during the cleaning step.

It should also be appreciated that the memory element may be placed atlocations other than between the M1 and M2 levels with respect to thesilicon surface. As such, the use of the terminology “M1” and “M2” isnot intended to restrict the memory element to locations between thefirst and second wiring levels above the silicon surface.

While the exemplary embodiment disclosed above is presented with respectto the problem of shunted magnetic memory elements, it is alsocontemplated that the principles described herein are also applicable toother semiconductor devices that require contact from above such asdiodes, ferroelectric memories and ovonics, to name a few. Furthermore,although the exemplary embodiment describes a lateral metal strap thatextends horizontally to connect to a via not directly below the memoryelement, the above process flow is also applicable to devices wherein avia is included directly beneath the memory element.

While the invention has been described with reference to a preferredembodiment or embodiments, it will be understood by those skilled in theart that various changes may be made and equivalents may be substitutedfor elements thereof without departing from the scope of the invention.In addition, many modifications may be made to adapt a particularsituation or material to the teachings of the invention withoutdeparting from the essential scope thereof. Therefore, it is intendedthat the invention not be limited to the particular embodiment disclosedas the best mode contemplated for carrying out this invention, but thatthe invention will include all embodiments falling within the scope ofthe appended claims.

INDUSTRIAL APPLICABILITY

The present disclosure has industrial applicability in the area ofsemiconductor device processing and, in particular, to the formation ofsemiconductor memory devices such as magnetic random access memory(MRAM).

1. A conductive line structure for a field effect transistor (FET) basedmagnetic random access memory (MRAM) device, comprising: a lateral metalstrap conductively coupled to a lower metallization line; a magnetictunnel junction (MTJ) stack formed on said metal strap; a metal shieldformed over said MTJ stack, said metal shield being self-aligned withrespect to said metal strap; and an upper metallization lineconductively coupled to said metal shield, wherein said metal shieldserves as an etch stop during the formation of said upper metallizationline.
 2. The structure of claim 1, wherein said MTJ stack furthercomprises: a non-magnetic layer formed between a lower magnetic layerand an upper magnetic layer; and a metal hardmask layer formed on saidupper magnetic layer; wherein the distance between said uppermetallization line and said upper magnetic layer is defined by a totalthickness of said metal hardmask layer and said metal shield.
 3. Thestructure of claim 2, wherein said total thickness of said metalhardmask layer and said metal shield is about 400 to about 500angstroms.
 4. The structure of claim 1, wherein said metal shieldcomprises one of: tantalum, tantalum nitride, titanium nitride,tungsten, platinum, and combinations comprising at least one of theforegoing.
 5. The structure of claim 1, wherein said metal hardmasklayer and said metal strap comprise one of: tantalum, tantalum nitride,titanium nitride, tungsten, platinum, and combinations comprising atleast one of the foregoing.
 6. The structure of claim 1, wherein: saidlower metallization line is formed at first metallization level (M1) ofthe MRAM device, and said upper metallization line is formed at a secondmetallization level (M2) of the MRAM device.
 7. The structure of claim1, further comprising: a wordline formed at a lower metallization level(M1) and adjacent said lower metallization line, said wordlineelectrically insulated from said lateral metal strap, and said wordlinedisposed below said MTJ stack; wherein said upper metallization linecomprises a bitline of an individual MRAM cell, said cell also includingsaid MTJ stack and said wordline.
 8. A method for forming the conductiveline structure of claim 1, the method comprising: forming a magneticstack layer over a metal underlayer, said metal underlayer in conductivecontact with said lower metallization line; forming a metal hardmasklayer over said magnetic stack layer; patterning said magnetic stacklayer and said metal hardmask layer so as to form said magnetic tunneljunction (MTJ) stack; encapsulating said MTJ stack with dielectricmaterial and planarizing said dielectric material to said metalhardmask; forming a metal shield layer over said dielectric material andsaid metal hardmask; patterning both said metal shield layer and saidmetal underlayer so as to form said metal shield that is self-alignedwith said metal strap; and forming said upper metallization line on saidmetal shield, wherein said metal shield serves as an etch stop duringthe formation of said upper metallization line.
 9. The method of claim8, wherein said metal hardmask layer is planarized to a thickness ofabout 200 angstroms prior to the formation of the metal shield layerthereupon.
 10. The method of claim 8, wherein said MTJ stack furthercomprises: a non-magnetic layer formed between a lower magnetic layerand an upper magnetic layer; and said a metal hardmask layer formed onsaid upper magnetic layer; wherein the distance between said uppermetallization line and said upper magnetic layer is defined by a totalthickness of said metal hardmask layer and said metal shield.
 11. Themethod of claim 10, wherein said total thickness of said metal hardmasklayer and said metal shield is about 400 to about 500 angstroms.
 12. Themethod of claim 11, wherein said metal hardmask layer is deposited at aninitial thickness of about 500 angstroms prior to planarization thereof.13. The method of claim 8, wherein said metal shield layer comprises oneof: tantalum, tantalum nitride, titanium nitride, tungsten, platinum,and combinations comprising at least one of the foregoing.
 14. Themethod of claim 8, further comprising: following said patterning of saidmetal shield layer and said metal underlayer, encapsulating saidself-aligned metal shield and said metal strap with an encapsulatingdielectric; and depositing an upper metallization level dielectric oversaid encapsulating dielectric.
 15. The method of claim 8, wherein saidconductive contact between said metal underlayer and a lowermetallization line is formed by a metal strap via.